SC Conference - Activity Details

Yan Solihin  (North Carolina State University)

Monday,  08:30AM - 12:00PM

Room D136

Cache designs are increasingly critical to the overall performance of computer systems, especially in the multicore and manycore design. In addition to the “memory wall” problem in which the memory access latency is too expensive to hide by the processor, there are other multicore-specific problems that are emerging. One problem is the “cache capacity contention” that occurs when multiple cores share the last level on-chip cache. Because current cache architecture uses core-oblivious management policies, unmanaged contention results in a huge performance volatility of many applications. Another problem is the “bandwidth wall”, a situation in which the lack of off-chip bandwidth limits the performance scalability of applications in future multicore systems. The bandwidth wall occurs due to the growth of transistor density dwarfing the growth of off-chip pin bandwidth by roughly 50% each year. Understanding these problems and solving them are important for system designers, HPC application developers, and performance tuners.