SC Conference - Activity Details
Future Scaling of Processor-Memory Interfaces
Authors:| Jung Ho Ahn (Hewlett-Packard) |
| Norm P. Jouppi (Hewlett-Packard) |
| Christos Kozyrakis (Stanford University) |
| Jacob Leverich (Stanford University) |
| Robert S. Schreiber (Hewlett-Packard) |
| Future HPC Architectures |
| Thursday, 03:30PM - 04:00PM |
| Room PB256 |
Continuous evolution in process technology brings energy-efficiency and reliability challenges, which are harder for memory system designs since chip multiprocessors demand high bandwidth and capacity, global wires improve slowly, and more cells are susceptible to hard and soft errors. Recently, there are proposals aiming at better main-memory energy efficiency by dividing a memory rank into subsets.
We holistically assess the effectiveness of rank subsetting in the context of system-wide performance, energy-efficiency, and reliability perspectives. We identify the impact of rank subsetting on memory power and processor performance analytically, then verify the analyses by simulating a chip-multiprocessor system using multithreaded and consolidated workloads. We extend the design of Multicore DIMM, one proposal embodying rank subsetting, for high-reliability systems and show that compared with conventional chipkill approaches, it can lead to much higher system-level energy efficiency and performance at the cost of additional DRAM devices.
The full paper can be found in the
ACM Digital Library and IEEE Computer Society
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