SC Conference - Activity Details
Performance Evaluation of NEC SX-9 using Real Science and Engineering Applications
Authors:| Takashi Soga (Tohoku University) |
| Akihiro Musa (NEC Corporation) |
| Youichi Shimomura (NEC Corporation) |
| Koki Okabe (Tohoku University) |
| Ryusuke Egawa (Tohoku University) |
| Hiroyuki Takizawa (Tohoku University) |
| Hiroaki Kobayashi (Tohoku University) |
| Ken'ichi Itakura (Japan Agency for Marine-Earth Science & Technology) |
| Perfomance Analysis and Optimization |
| Thursday, 10:30AM - 11:00AM |
| Room D135-136 |
This paper describes a new-generation vector parallel supercomputer, NEC SX-9 system.
The SX-9 processor has an outstanding core to achieve over 100Gflop/s, and a software-controllable on-chip cache to keep the high ratio of the memory bandwidth to the floating-point operation rate.
Moreover, its large SMP nodes of 16 vector processors with 1.6Tflop/s performance and 1TB memory are connected with dedicated network switches, which can achieve inter-node communication at 128GB/s per direction.
The sustained performance of the SX-9 processor is evaluated using six practical applications in comparison with conventional vector processors and the latest scalar processor such as Nehalem-EP.
Based on the results, this paper discusses the performance tuning strategies for new-generation vector systems.
An SX-9 system of 16 nodes is also evaluated by using the HPC challenge benchmark suite and a CFD code.
Those evaluation results clarify the highest sustained performance and scalability of the SX-9 system.
The full paper can be found in the
ACM Digital Library and IEEE Computer Society
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