SC Conference - Activity Details

Subhash Saini  (NASA Ames Research Center)

Andrey Naraikin  (Intel Corporation)

Rupak Biswas  (NASA Ames Research Center)

David Barkai  (Intel Corporation)

Timothy Sandstrom  (NASA Ames Research Center)

Perfomance Analysis and Optimization

Thursday,  11:00AM - 11:30AM

Room D135-136

In this paper, we present an early performance evaluation of a 512-core cluster based on Intel third-generation quad-core processor—the Intel® Xeon® 5500 Series (code named Nehalem-EP). This is Intel's first processor with non-uniform memory access (NUMA) architecture managed by on-chip integrated memory controllers. It employs a point-to-point interconnect called Quick Path Interconnect (QPI) between processors and to the input/output (I/O) hub. Two other features of the processor are the introduction of simultaneous multi threading (SMT) to Intel quad-core and "Turbo Mode"—the ability to dynamically increase the clock frequency as long as the power consumed remains within the designed thermal envelope. We critically evaluate all these Nehalem features using the High Performance Computing Challenge (HPCC) benchmarks, NAS Parallel Benchmarks (NPB), and four full-scale scientific applications. We compare and contrast Nehalem results against an SGI Altix ICE 8200EX® platform and an Intel® cluster of previous generation processors.

The full paper can be found in the ACM Digital Library and IEEE Computer Society