SC Conference - Activity Details

Marghoob Mohiyuddin  (University of California, Berkeley / Lawrence Berkeley National Laboratory)

Mark Murphy  (University of California, Berkeley)

Leonid Oliker  (Lawrence Berkeley National Laboratory)

John Shalf  (Lawrence Berkeley National Laboratory)

John Wawrzynek  (University of California, Berkeley)

Samuel Williams  (Lawrence Berkeley National Laboratory)

Future HPC Architectures

Thursday,  04:00PM - 04:30PM

Room PB256

As power has become the pre-eminent design constraint for future HPC systems, computational efficiency is being emphasized over simply peak performance. Recently, static benchmark codes have been used to find a power efficient architecture. Unfortunately, because compilers generate sub-optimal code, benchmark performance can be a poor indicator of the performance potential of architecture design points. Therefore, we present hardware/software co-tuning as a novel approach for system design, in which traditional architecture space exploration is tightly coupled with software auto-tuning for delivering substantial improvements in area and power efficiency. We demonstrate the proposed methodology by exploring the parameter space of a Tensilica-based multi-processor running three of the most heavily used kernels in scientific computing, each with widely varying micro-architectural requirements: sparse matrix vector multiplication, stencil-based computations, and general matrix-matrix multiplication. Results demonstrate that co-tuning significantly improves hardware area and energy efficiency -- a key driver for next generation of HPC system design.

The full paper can be found in the ACM Digital Library and IEEE Computer Society