SC Conference - Activity Details

Shekhar Srikantaiah  (Pennsylvania State University)

Reetuparna Das  (Pennsylvania State University)

Asit K. Mishra  (Pennsylvania State University)

Chita R. Das  (Pennsylvania State University)

Mahmut Kandemir  (Pennsylvania State University)

Cache Techniques

Tuesday,  02:00PM - 02:30PM

Room PB255

This paper examines an operating system directed integrated processor-cache partitioning scheme that partitions both the available processors and the shared last level cache in a chip multiprocessor among different multi-threaded applications. Extensive simulations using a full system simulator and a set of multiprogrammed workloads show that our integrated processor-cache partitioning scheme facilitates achieving better performance isolation as compared to state of the art hardware/software based solutions. Specifically, our integrated processor-cache partitioning approach performs, on an average, 20.83% and 14.14% better than equal partitioning and the implicit partitioning enforced by the underlying operating system, respectively, on the fair speedup metric on an 8 core system. We also compare our approach to processor partitioning alone and a state-of-the-art cache partitioning scheme and our scheme fares 8.21% and 9.19% better than these schemes on a 16 core system.

The full paper can be found in the ACM Digital Library and IEEE Computer Society